- Titel
- A 2TnC ferroelectric memory gain cell suitable for compute-in-memory and neuromorphic application
- Zitierfähige Url:
- https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa2-796468
- Konferenz
- International Electron Devices Meeting (IEDM). San Francisco, 07. -11.Dez. 2019
- Quellenangabe
- 2019 IEEE International Electron Devices Meeting (IEDM)
; Proceedings
Erscheinungsort: New York, NY
Verlag: IEEE
Erscheinungsjahr: 2020
Seiten: 38.6.1-38.6.4 - Erstveröffentlichung
- 2020
- Abstract (EN)
- A 2TnC ferroelectric memory gain cell consisting of two transistors and two or more ferroelectric capacitors (FeCAP) is proposed. While a pre-charge transistor allows to access the single cell in an array, the read transistor amplifies the small read signals from small-scaled FeCAPs that can be operated either in FeRAM mode by sensing the polarization reversal current, or in ferroelectric tunnel junction (FTJ) mode by sensing the polarization dependent leakage current. The simultaneous read or write operation of multiple FeCAPs is used to realize compute-in-memory (CiM) algorithms that enable processing of data being represented by both, non-volatilely internally stored data and externally applied data. The internal gain of the cell mitigates the need for 3D integration of the FeCAPs, thus making the concept very attractive especially for embedded memories. Here we discuss design constraints of the 2TnC cell and present the proof-of-concept for realizing versatile (CiM) approaches by means of electrical characterization results.
- Andere Ausgabe
- Link zum Artikel, der zuerst in der IEEE Xplore Digital Library erschienen ist:
DOI: 10.1109/IEDM19573.2019.8993663 - Freie Schlagwörter (DE)
- Ferroelektrische 2TnC-Speicherverstärkungszelle, ferroelektrische Kondensatoren, FeCAP, Vorladetransistor, Lesetransistor, ferroelektrischer Tunnelübergang, polarisationsabhängiger Leckstrom, Compute-in-Memory-Algorithmen, eingebettete Speicher
- Freie Schlagwörter (EN)
- 2TnC ferroelectric memory gain cell, ferroelectric capacitors, FeCAP, pre-charge transistor, read transistor, ferroelectric tunnel junction, polarization dependent leakage current, compute-in-memory algorithms, embedded memories
- Klassifikation (DDC)
- 621.3
- Verlag
- IEEE, New York, NY
- Förder- / Projektangaben
- Europäische Union (EU)
Europäischer Fonds für regionale Entwicklung (EFRE) - Version / Begutachtungsstatus
- angenommene Version / Postprint / Autorenversion
- URN Qucosa
- urn:nbn:de:bsz:14-qucosa2-796468
- Veröffentlichungsdatum Qucosa
- 20.06.2022
- Dokumenttyp
- Konferenzbeitrag
- Sprache des Dokumentes
- Englisch
- Lizenz / Rechtehinweis
