- AutorIn
- Ahmedullah Aziz
- Evelyn T. BreyerNanoelectronic Materials Laboratory GmbH, Dresden
- An Chen
- Xiaoming Chen
- Suman Datta
- Sumeet Kumar Gupta
- Michael Hoffmann
- Xiaobo Sharon Hu
- Adrian Ionescu
- Matthew Jerry
- Thomas Mikolajick
- Halid Mulaosmanovic
- Kai Ni
- Michael Niemier
- Ian O'Connor
- Atanu Saha
- Stefan Slesazeck
- Sandeep Krishna Thirumala
- Xunzhao Yin
- Titel
- Computing with Ferroelectric FETs
- Untertitel
- Devices, models, systems, and applications
- Zitierfähige Url:
- https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa2-768385
- Konferenz
- Design, Automation & Test in Europe Conference & Exhibition (DATE). Dresden, 19. - 23. März 2018
- Quellenangabe
- 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Erscheinungsort: New York, NY
Verlag: IEEE
Seiten: 1289-1298 - Erstveröffentlichung
- 2018
- Abstract (EN)
- In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect to all of the aforementioned operating modes). These device-level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.
- Andere Ausgabe
- Link zum Artikel, der zuerst in der IEEE Xplore Digital Library erschienen ist
DOI: 10.23919/DATE.2018.8342213 - Freie Schlagwörter (DE)
- Eisen, Transistoren, Kapazität, Mathematisches Modell, Schalter, Logische Gatter
- Freie Schlagwörter (EN)
- Iron, Transistors, Capacitance, Mathematical model, Switches, Logic gates
- Klassifikation (DDC)
- 621.3
- Verlag
- IEEE, New York, NY
- Förder- / Projektangaben
- National Science Foundation (NSF)
ID: 1640081 - Nanoelectronics Research Corporation (NERC)
Extremely Energy Efficient Collective Electronics (EXCEL)
ID: 2698.004 - Europäischer Fond für regionale Entwicklung (EFRE)
- Version / Begutachtungsstatus
- angenommene Version / Postprint / Autorenversion
- URN Qucosa
- urn:nbn:de:bsz:14-qucosa2-768385
- Veröffentlichungsdatum Qucosa
- 30.11.2021
- Dokumenttyp
- Konferenzbeitrag
- Sprache des Dokumentes
- Englisch
- Lizenz / Rechtehinweis