Emerging Silicon Nanowire Transistors: Design, Fabrication, Characterization, and Sensing Applications

Sayantan Ghosh

AutorIn

Sayantan Ghosh

Titel

Emerging Silicon Nanowire Transistors: Design, Fabrication, Characterization, and Sensing Applications

Zitierfähige Url:

https://nbn-resolving.org/urn:nbn:de:bsz:14-qucosa2-1054021

Erstveröffentlichung

2026

Datum der Einreichung

17.07.2025

Datum der Verteidigung

18.12.2025

Abstract (EN)

As semiconductor technologies approach the sub-nm node, conventional CMOS scaling encounters fundamental limitations. To address these challenges, novel materials and device concepts are explored to enable further performance enhancement. Among these, field-effect transistors (FETs) based on nanowire and nanosheet architectures have emerged as leading candidates for future ultra-scaled transistors. Silicon (Si) nanowires, in particular, with their compact nanoscale geometry and high surface-to-volume ratio, enable excellent electrostatic control across the channel, offering clear advantages for advanced logic devices and a broad range of innovative sensing applications. This thesis explores two state-of-the-art Si nanowire-based device concepts: Reconfigurable Field-Effect Transistors (RFETs) and Junctionless Nanowire Transistors (JNTs). CMOS-compatible, top-down fabrication processes are developed to realize high-quality Si nanowire devices with precise control over nanowire geometry, contact engineering, and gate stack integration. A novel mixed-dimensional RFET is demonstrated in this work by integrating a one dimensional (1D) Si nanowire channel with a two-dimensional (2D) hexagonal boron nitride (hBN) dielectric. The resulting devices exhibit dynamic reconfigurability, enabling switching between p- and n-type operation via appropriate gate biasing. The transfer characteristics observed under various gating architectures show improved subthreshold swing, reduced hysteresis, and enhanced on-currents for both carrier types, attributed to the encapsulation and passivation of the nanowire by the hBN flake. This mixed-dimensional approach improves electrostatic gate control and overall device performance. In addition to RFETs, this work investigates JNTs, realized using highly n-type doped Si nanowires without the formation of p-n junctions, where carrier transport is modulated electrostatically by the gate. Long-channel JNTs are engineered to exhibit both ambipolar and unipolar behavior through back and top gate biasing, enabling effective polarity control and tunable transfer characteristics with on/off current ratios spanning up to eight orders of magnitude. This ambipolarity is further exploited for gas sensing applications, where exposure to varying concentrations of NO2 and NH3 induces distinct shifts in the transfer curves, and systematic modulation of p- and type on-currents. Furthermore, short-channel JNTs with channel lengths down to 50 nm demonstrate excellent electrostatic control and scalability, achieving on/off ratios exceeding 10^6, and a subthreshold swing of about 200 mV/dec. Overall, this work advances the fundamental understanding and practical implementation of emerging Si nanowire transistor technologies by providing novel insights into device physics, demonstrating scalable and CMOS-compatible fabrication methodologies, and highlighting the potential of these architectures for real-world sensing applications.

Freie Schlagwörter (EN)

Silicon Nanowire Transistors, Reconfigurable Field-Effect Transistors (RFETs), Junctionless Nanowire Transistors (JNTs), Hexagonal Boron Nitride (hBN), Gas Sensing, Schottky Barrier Transistors, Polarity Control,

Klassifikation (DDC)

621

Klassifikation (RVK)

ZN 3700

GutachterIn